1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which can electrically rewrite data.
2. Description of the Related Art
Conventionally, EPROMs (erasable programmable read-only memories) and EEPROMs (electrically erasable programmable read-only memories) have been generally used as nonvolatile semiconductor memory devices allowing a user to rewrite data stored therein. In an EPROM, data is written by using a write device called "programmer (writer)" and the data stored in all of the memory cells is simultaneously erased by the irradiation of ultraviolet light. Since the EPROM can use a single transistor/single cell structure allowing reduction in area per memory cell, the EPROM is advantageous in that a larger number of memory cells can be easily integrated to realize a larger storage capacity, and less cost per bit. However, since the EPROM requires use of a ceramic package including expensive quartz glass for irradiating UV rays at the time of the erase operation, the cost reduction per chip has limitations. In addition, since a dedicated write device is used for writing data, a chip mounting such a device thereon must be installed into a system via a socket enabling the removal/installation of the chip. Thus, the EPROM is disadvantageous in that the removal/installation of the chip for a write operation is troublesome and that the mounting cost required of such a chip is higher.
On the other hand, an EEPROM is advantageous in that the EEPROM can electrically write or erase data while being permanently installed into the system. However, the EEPROM enables the write and the erase of data on a bit basis and thus requires a select transistor for each memory cell. Consequently, the area per memory cell of the EEPROM becomes one and a half times to twice as large as that of the EPROM so that the cost per bit increases. Thus, the EEPROM is disadvantageous for realizing a larger-capacity memory device.
In order to solve such problems, a flash memory has been developed as a nonvolatile semiconductor memory device having the advantages of the EPROM in combination with those of the EEPROM. As shown in FIG. 8, the memory cell of such a flash memory is implemented as a cell transistor having a floating gate type FET structure in which a floating gate FG is disposed in a gate oxide film, provided under the control gate CG of a MOSFET (metal-oxide-semiconductor field effect transistor), so as to be insulated from the control gate CG, as disclosed in U.S. Pat. Nos. 5,249,158 and 5,245,570, for example. The floating gate type cell transistor has a similar structure to that of an EPROM or an EEPROM. However, the flash memory simultaneously erases data stored in such cell transistors on a chip basis or on a block basis, thereby obviating the memory cell select transistors and enabling a single transistor/single cell structure. Thus, the cost per bit of the flash memory becomes as inexpensive as that of the EPROM, and the flash memory is suitable for realizing a larger-capacity memory device. In addition, since the flash memory can electrically write and erase data in the same way as the EEPROM, an inexpensive plastic package can be used therefor and it is no longer necessary to remove and install a chip therefrom/thereto unlike the EPROM. The flash memory is generally formed as a NOR type in which cell transistors are connected to a bitline one by one or as a NAND type in which a plurality of serially connected cell transistors are simultaneously connected to a bitline. Though a flash memory of a NAND type has lower read speed when random access is performed, the flash memory is advantageous in that the area per memory cell can be further reduced because the area required for connecting cell transistors to a bitline can be reduced as compared with a flash memory of a NOR type. It is noted that flash memories of an AND type and flash memories of a DINOR type have also been proposed. However, in the flash memories of the AND type and the DINOR type, the electrons are injected into and drained from the floating gate FG at the times of an erase operation and a write operation, respectively, in the opposite manner to that of the flash memories of the NOR type and the NAND type. Thus, in the following description, only the flash memories of the NOR type and the NAND type will be described.
The cell transistor of the flash memory stores data representing whether or not electrons have been accumulated in the floating gate FG thereof as "0" or "1", respectively. More specifically, when the data is read out from a cell transistor of the flash memory, the source S thereof is grounded (=0 V), a low voltage of about 1 V is applied to the drain D thereof and a power supply voltage VCC (generally about 5 V) is applied to the control gate CG thereof. Then, if electrons have not been accumulated in the floating gate FG, the drain D becomes conductive with the source S so that drain current (or channel current) flows between the drain D and the source S because the threshold voltage of the cell transistor is low. On the other hand, if electrons have been accumulated in the floating gate FG, then the threshold voltage of the cell transistor becomes higher. As a result, the drain D remains isolated from the source S so that drain current hardly flows therebetween. Thus, by detecting the level of the drain current, the data stored in the cell transistor can be read out. As mentioned above, the voltage applied to the drain D at the time of the read operation is set at as low as about 1 V. Such an application of a low voltage is intended for preventing a case where a parasitic weak write (soft write) occurs owing to the application of a high voltage. It is noted that, in the following description, the data "0" represents a state where electrons have been accumulated in the floating gate FG and a threshold voltage is high and the data "1" represents a state where electrons have not been accumulated in the floating gate FG and a threshold voltage is low.
When the data stored in the cell transistor of the flash memory is erased, a high voltage of about 12 V is applied to the source S and the control gate CG is grounded. Then, a high electric field is generated between the floating gate FG and the source S so that the electrons accumulated in the floating gate FG are drained by a tunnel current via a thin gate oxide film. As a result, the threshold voltage of the cell transistor is decreased, the cell transistor is initialized into a state where the data "1" is stored and the data is erased. The data is erased simultaneously on a chip basis or on a block basis, as described above.
However, in such an erase method, since a high voltage is applied to the source S, the source junction must have an increased withstand voltage. Thus, it becomes more difficult to fabricate the source electrode because a finer fabrication technique is required for the source electrode. In addition, a part of the hot holes generated in the vicinity of the source junction are trapped into the gate oxide film so that the reliability of the cell transistor is disadvantageously degraded. Thus, a negative gate erase method in which a power supply voltage VCC (generally about 5 V) is applied to the source and a negative voltage of about -10 V is applied to the control gate CG, thereby draining the electrons accumulated in the floating gate FG by a tunnel current has also been proposed. According to the negative gate erase method, since the voltage to be applied to the source S becomes lower, the withstand voltage of the source junction can be advantageously reduced and the gate length of the cell transistor can be advantageously shortened. In the erase method in which a high voltage is applied to the source S, since the inter-band tunnel current flowing at the time of the erase operation reaches as high as several mA on the entire chip, a generally used booster circuit having a low current supply ability cannot supply such a high voltage and thus a high erase voltage Vpp must be supplied from an external power supply. On the other hand, in the case of employing the negative gate erase method, since the power supply voltage VCC has only to be applied to the source S, a single power supply erase operation requiring only the supply of the power supply voltage VCC to the flash memory is realized relatively easily.
When data is written to the cell transistor of the flash memory, a high voltage of about 12 V is applied to the control gate CG, the source S is grounded (=0 V) and a voltage of about 7 V is applied to the drain D. Then, a large amount of current flows between the drain D and the source S so that the high-energy hot electrons generated in the vicinity of the drain junction are injected into the floating gate FG and accumulated therein. As a result, the data "0" is stored. In other words, the data write operation can only rewrite the initialized data "1" of the cell transistor into "0" and cannot rewrite the data "0" into "1". Thus, when the data stored in the cell transistors is rewritten in the flash memory, an erase operation is first performed, thereby initializing once the data stored in the cell transistors within the chip or the block. Thereafter, the write operation must be performed by selecting only the cell transistors in which the data "0" are to be stored.
It is noted that, in such a method in which the electrons are injected into the floating gate FG by using the hot electrons, a large amount of current of about 1 mA is required to be supplied to the cell transistors at the time of the write operation. Thus, a flash memory in which the current required of the write operation is reduced by the injection of the electrons using FN tunnel current in the same way as in a common EEPROM has also been developed.
Moreover, in the cell transistor of the flash memory, the write operation is performed in the vicinity of the drain junction, and the erase operation is performed in the vicinity of the source junction. Thus, in designing such a device, the profiles of these junctions are preferably optimized in accordance with the respective operations. More specifically, the cell transistor preferably has an asymmetric structure between the drain junction and the source junction in which an electric field concentrated profile is used for the drain junction in order to improve the write efficiency, and an electric field dispersed profile is used for the source junction in order to enable the application of a high voltage at the time of the erase operation.
Furthermore, since various types of battery-driven portable electronic equipment have become more and more popular, and finer semiconductor fabrication processes have been realized in recent years, it is desirable to reduce the power supply voltage for driving a semiconductor device. Reflecting such tendencies, various semiconductor devices requiring a power supply voltage VCC reduced from 5 V to 3.3 V have recently been the subject of intense development. As a result, flash memories of the above-described type requiring a power supply voltage of 3.3 V have also been developed. However, under current circumstances, even in such a flash memory requiring a power supply voltage of 3.3 V, the voltage to be applied to the control gate CG of the cell transistor during a read operation is still set at about 5 V, which has been boosted from the power supply voltage VCC of 3.3 V by a word line booster circuit provided inside the chip, for accelerating the operating speed and sufficiently enlarging the operating margin.
Unlike a RAM (random access memory) and the like, the flash memory has a lot of operation states including not only the data write and read operations, but also a block erase operation, a chip simultaneous erase operation and a read operation from a status register. Thus, if any of these operation states is to be specified by combining externally supplied control signals such as a chip enable signal /CE, a write enable signal /WE and an output enable signal /OE, new control signals should be determined in addition to the control signals of a conventional EPROM or EEPROM, and additional input terminals associated with the respective control signals should also be provided. In such a case, the flash memory cannot be used conveniently. Thus, in flash memories currently in use, each of the operation states is specified not by the combination of control signals, but mainly by the combination of data and addresses to be input as a command. In such a flash memory, a command state machine CSM determines the type of an externally input command, and a write state machine WSM executes a corresponding operation in response to the command.
Furthermore, the flash memories performing the erase operation on a block basis use either blocks (or erase blocks) of unequal sizes or blocks of an equal size (U.S. Pat. No. 5,245,570). In such a flash memory including a plurality of blocks, a BP (block protect) data storage region for storing BP data therein is sometimes provided for each of the blocks in order to protect the data stored in each block. In this case, if the BP data is stored in the BP data storage region, then the erase and the write of data from/into the block are prohibited in principle. Also, such a flash memory includes a /WP input terminal for inputting an externally supplied write protect signal /WP. The write protect signal /WP is a control signal to validate the BP data stored in the BP data storage region in each block when activated (L level) and to invalidate the BP data when deactivated (H level). Thus, only when the write protect signal /WP to be input to the /WP input terminal has been activated (L level), the erase operation and the write operation are prohibited with respect to a block in which the BP data is stored in the BP data storage region. In the other cases, the erase operation and the write operation can be executed.
It is noted that a WP set command and a WP release command are sometimes provided instead of providing such a /WP input terminal. That is to say, when a WP set command is input by the above-described command input method, a WP signal inside the device is activated (H level). On the other hand, when a WP release command is input, the WP signal is deactivated (L level), thereby controlling the validity and invalidity of the BP data. Such a command input method obviates the /WP input terminal and realizes a compatibility with the input terminal of a conventional EPROM or EEPROM.
However, in the cell transistor of the flash memory, when an excessive erase results from the drainage of an excessive amount of electrons from the floating gate FG during the erase operation, the threshold voltage of the cell transistor becomes a negative voltage. If the threshold voltage of the cell transistor becomes a negative voltage in such a manner, then leak current also flows from a non-selected cell transistor because a select transistor for selecting a cell transistor is not provided. As a result, it is no longer possible to correctly read the data out from another cell transistor selected on the same bitline and therefore, a critical defect is caused in the flash memory.
Thus, in order to prevent such excessive erasing during the erase operation, the flash memory first performs a "program before erase", thereby accumulating electrons in the floating gates FG of all of the cell transistors from which the data are to be erased (or writing the data "0") and preventing the electrons from being forcibly drained from the floating gates FG of the remaining cell transistors in which the electrons have not been accumulated by the erase operation. Thereafter, the erase operation by the application of a high voltage or the like is performed for a short time and then an erase verification operation is performed to determine whether or not the erase operation has been completely performed. The erase verification operation is repeatedly performed until a cell transistor from which the data has not been erased sufficiently no longer exists, thereby preventing the erase operation from being performed for a longer time than necessary.
Thus, the flash memory requires an extremely long time (on the order of several hundreds of milliseconds) for the erase operation. It is rather possible that the erase operation is forced to end in the middle thereof by a cutoff of power or the input of a device reset signal. If the erase operation ends abnormally in the middle thereof, all the data stored in the cell transistors is not initialized into "1" (small threshold voltage) but some of the data may remain "0" (large threshold voltage) in some cases. Herein, the write operation is performed only by rewriting the initialized stored data "1" into "0", as described above. Thus, when the data "1" is desired to be written, the initialized data "1" stored in the cell transistors is actually left as it is. Thus, if there are some cell transistors in which the data has not been initialized but remains "0", then it is impossible to write data "1" into such cell transistors.
As a result, in a conventional flash memory, it is necessary to always keep in mind the possibility that the data has not been erased completely during the write operation after the erase operation of data has been performed, and therefore a program of a system using such a flash memory is adversely complicated. Consequently, the procedure for operating a conventional flash memory is disadvantageously troublesome. That is to say, even if one tries to detect an abnormal end of an erase operation before a write operation is performed, a conventional flash memory provides no means for easily enabling such a detection. For example, a bit ES indicating whether the erase has succeeded or failed is provided for a status register of a flash memory. However, if the power is cut off or a device reset signal is input, then the status register is also reset. Thus, in such a case, the abnormal end cannot be detected by the status register. Therefore, in order to detect such an abnormal end of the erase operation, there is no means other than reading out all the data from all the memory cells and verifying the normal erase thereof one by one. Further-more, in the case where a write operation has been performed, a rewrite operation is repeatedly performed until it is determined by the write verification that the data "0" has been written correctly. However, if the write of the data "1" is disabled by the abnormal end of the erase operation, the rewrite operation cannot be performed and another error correction procedure is required.
In addition, the BP data storage region in each block is generally a region for storing one bit of BP data therein. Therefore, when the data stored in the block is erased, the BP data is also cleared and an erase/write enable state is re-established. However, in the erase operation, the data "0" is written by the program before erase operation and then initialized into "1", as described above. Thus, if the erase operation abnormally ends on any stage thereof because of the abnormality of a power supply potential or the influence of a noise, the BP data is erroneously written into the BP data storage region irrespective of whether the BP data is "0" or "1". As a result, there is a possibility that an erase/write disable state is unintentionally caused. For example, assuming that the data "1" initialized by the erase operation represents an erase/write enable state and "0" represents the BP data, the abnormal end of the erase operation immediately after the program before erase causes the BP data to be stored in the BP data storage region. Moreover, in this case, if the /WP signal input to the /WP input terminal has been activated (L level) or the WP signal has been activated (H level) by the input of a WP set command, then the /WP signal must be deactivated (H level) or the WP signal must be deactivated (L level) by the input of a WP release command, and then the erase operation must be performed again.
Consequently, in order to simply perform again an erase operation even in the case where the BP data is stored in the BP data storage region and an erase/write disable state is caused because of the abnormal end of the erase operation, a circuit for switching the /WP signal to be input to the /WP input terminal or an error correction routine for inputting a WP release command must be additionally provided for a conventional flash memory. As a result, the circuit configuration or the program of a system using such a flash memory is disadvantageously complicated.